The bitmap was saved to 80x60 at 8bpp, allowing the pixel values to index character tiles from a character generator ROM in VHDL. This design slightly improves on my previous project by accounting for the clock delay incurred with the registered address into the BRAM.
It's not a very good picture, using an old USB capture device which actually goes from VGA through a converter to analog video before it hits the USB device. Cell phone camera will take a better picture.
The tile calculation formula maps an 80x60 tile display of 8x8 character tiles to a 640x480 VGA display. The present design is far from optimized and uses integer math to convert the pixel scan location to a tile address in the simulated VRAM. The synthesis tool infers a DSP to implement a multiplier. The Vivado DRC (design rule checker) flags this DSP implementation with warnings which I would like to eliminate.
